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| pbl 3796, pbl 3796/2 subscriber line interface circuit description pbl 3796 is an analog subscriber line interface circuits (slics), which are fabrica- ted in a 75 v bipolar, monolithic process. the programmable battery feed is resistive with short-loop current limiting. a switch-mode regulator reduces on-chip power dissipation in the active state. in the standby state, power dissipation is further reduced, while still permitting supervisory functions to be active. tip-ring polarity is reversible without altering slic supervisory and voice frequency (vf) functions. tip and ring outputs can be set to high impedance states. these and other operating states are activated via a parallel, four bit control word. an external resistor controls the off-hook detector threshold current. the ring trip detector can operate with both balanced and unbalanced ringing systems. the two detectors are read via a shared output. ring and test relay drivers with internal clamp diodes are provided. the complex or real two-wire impedance is set by a scaled, lumped element network. two- to four-wire and four- to two-wire signal conversion is provided by the slic in conjunction with either a conventional or a programmable codec/filter. longitudinal line voltages are suppressed by a control loop within the slic. packages are 28-pin, dual-in-line; 32-pin or 44-pin j-leaded chip carrier. the difference between pbl 3796 and pbl 3796/2 is mainly the longitudinal balance spec. key features ? on-chip switch mode regulator to minimize power dissipation ? programmable, resistive battery feed with short-loop current limiting ? line feed characteristics independent of battery variations ? tip-ring polarity reversal function ? tip and ring open circuit state; tip open with ring active state ? detectors: - programmable loop current detector - ring trip detector ? ring and test relay drivers ? line terminating impedance, complex or real, set by a simple external network ? hybrid function with conventional or programmable codec/filters ? 70 db longitudinal to metallic balance ? 79 ma peak longitudinal current suppression ? idle noise < 10 dbrnc, < -80 dbup figure 1. block diagram. pin numbers refer to the dual-in-line package. april 1997 input decoder and control loop detector vf signal transmission line feed controller and longitudinal suppression switching regulator two-wire interface ring relay driver test relay driver ring trip comparator 4 5 26 25 27 22 23 28 2 6 7 1 ringrly testrly dr dt tipx hpt hpr ringx l gnd2 vbat vreg 8 910320 vqbat chs chclk vcc vee 16 14 15 11 12 13 24 21 19 17 18 c1 c2 c3 c4 e0 det rd vtx rsn rdc gnd1 4-105 pbl 3796 pbl 3798/5 pbl 3796 pbl 3796
4-106 pbl 3796 absolute maximum ratings note: pin numbers refer to the 28-pin, dual-in-line package, unless otherwise indicated. parameter symbol min max unit temperature and humidity storage temperature range t stg -55 +150 c operating ambient temperature range t amb -40 +85 c operating junction temperature range (note 1) t j -40 135 c power supply v cc with respect to ground v cc -0.4 +6.5 v v ee with respect to ground v ee -6.5 +0.4 v v bat with respect to ground v bat -70 +0.4 v power dissipation continuous power dissipation at t amb = 70 c (note 3) 28-pin, plastic dual-in-line (n) 1.5 w 44-pin j-leaded chip carrier (qn) 1.5 w 32-pin, j-leaded and leadless chip carrier (rn) 1.7 w ground voltage between gnd1 and gnd2 (note 4) v g12 -0.1 +0.1 v switch mode regulator peak current through regulator switch (pin l) i lpk 150 ma regulator switch output (pin l) peak off-state voltage v lpk +2 v relay drivers test relay supply voltage v trly v bat v cc v ring relay supply voltage v rrly v bat v cc v test relay current i trly 80 ma ring relay current i rrly 80 ma ring trip comparator input voltage v dt , v dr v bat 0v input current, t p = 10 ms i dt , i dr -2 +2 ma digital inputs, outputs c1 - c4, e0, det, chclk input voltage v id -0.4 v cc v output voltage (det not active) v od -0.3 v cc v output current i od 3ma tipx and ringx terminals tipx or ringx continuous voltage (notes 5, 6) v t , v r -70 1 v tipx or ringx, pulsed voltage, t w < 10 ms and t rep > 10 s (notes 5, 6) v t , v r -70 5 v tipx or ringx, pulsed voltage, t w < 1 m s and t rep > 10 s (notes 5, 6) v t , v r -90 10 v tipx or ringx, pulsed voltage, t w < 250 ns and t rep > 10 s (notes 5, 6, 7) v t , v r -120 15 v tipx or ringx current i ldc -105 105 ma recommended operating conditions parameter symbol min max unit ambient temperature t amb 070 c case temperature t case 090 c v cc with respect to ground v cc 4.75 5.25 v v ee with respect to ground v ee -5.25 -4.75 v v bat with respect to ground (note 8, 9, 11) v bat -58.0 -40.0 v gnd2 with respect to gnd1 (note 10) v g12 00 v 4-107 pbl 3796 electrical characteristics 0 c t amb 70 c, v cc = +5 v 5%, -58.0 v v bat -46.0 v,v ee = -5v 5%, gnd1 = gnd2, r dc1 = r dc2 = 1.25 k w , r d = 51.1 k w , r ch = 909 w , r bat = 10 w , c hp = 0.22 m f, c dc = 1.2 m f, c d = 0.01 m f, c tc = c rc = 2200 pf, c ch1 = 0.047 m f, c ch2 = 1500 pf, c flt = 0.47 m f, c bat = 0.47 m f, c q = 0.33 m f, l = 1mh; z tr (2-wire ac terminating impedance) = 600 w , z l (line impedance) = 600 w , r f1 = r f2 = 0 ohm, r t = 60 k w , r rx = 30 k w ; unless otherwise specified. the specifications are with respect to exact external component values. ref parameter fig condition min typ max unit 2-wire port overload level, v tro 2 1% thd, e l = 0, f = 1 khz, 3.1 3.5 v pk (note 1) 7.2 8.3 dbm 9.0 10.1 dbu v bat = -46.0 v to -58.0v 1% thd, 1 khz rl dc =2000 w , rl ac =600 w 1.55 3 vpk rl dc = , rl ac =600 w 1.5 vpk v bat = -43.5 v to -46.0v 1% thd, 1 khz +25 c to +70 c rl dc =2000 w , rl ac =600 w 2 vpk v bat = -43.5 v to -46.0v 1% thd, 1 khz 0 c to +25 c rl dc =2000 w , rl ac =600 w 1 vpk input impedance, z trx note 3 longitudinal impedance, z lot , z lor 3f 100 hz 25 40 w /wire longitudinal current limit, i lot , i lor f 100 hz active state 20 28 ma rms /wire stand-by state 8.5 19 ma rms /wire longitudinal to metallic balance, b lm ieee standard 455-1985 0.2 khz < f < 3.4 khz, note 4 standard version normal polarity 50 70 db reversed polarity 50 65 db -/2 version normal polarity 60 70 db reversed polarity 55 65 db average per lot, normal polarity 65 db metallic to longitudinal balance, b ml fcc part 68 paragraph 68.310 0.2 khz< f <4.0 khz 40 db f = 1.0 khz 53 db notes 1. the circuit includes thermal protection. ref. to section over-temperature protection. operation above 135 c may degrade device reliability. 2. C 3. values apply for momentary junction temperature of 120 c without heat sink. 4. the gnd1 and gnd2 pins should be connected together via a direct printed circuit board trace. 5. v t and v r are referenced to ground. t w is pulse width of a rectangular test pulse and t rep is pulse repetition rate. 6. these voltage ratings require a diode to be installed in series with the vbat pin as shown in figure 11 (d 7 ). 7. r f1 , r f2 3 20 w is also required. pulse is supplied to tip and ring outside r f1 , r f2 . 8. for long loop applications with -63v< v bat < -56v, the saturation guard reference voltage, v sgref , should be adjusted by calculating a value for resistor r sg as described in the text. not that the adjustment terminal, rsg, is available only on the 44-pin leaded chip carrier packages. 9. v bat should be applied with a ? v bat / ? t < 4 v/ m sec. a time constant of 2.6 m s is suggested (e.g. 5.6 w and 0.47 m f). the vbat terminal must at all times be at a lower potential than any other terminal to maintain proper junction isolation. refer to sect ion power-up sequence. 10. gnd1 and gnd2 must be connected before supply voltages. 11. a vbat of maximum -40v may be used. however with a vbat of -40 to -46 v, the performance on long lines* will degrade outside the specified limits. parameters effected are; line current, longitudinal balance, idle channel noise and vbat psrr. *long lines is in this case outside the constant current range with the vbat dependant saturation guard activated. 4-108 pbl 3796 ref parameter fig conditions min typ max unit figure 5. metallic-to-longitudinal (b mle ) and four-wire-to-longitudinal (b fle ) balance. 1/ w c << 150 w , r lt = r lr = 300 w , r t = 60 k w , r rx = 30 k w . figure 4. longitudinal-to-metallic (b lme ) and longitudinal-to-four-wire (b lfe ) balance. 1/ w c << 150 w , r lt = r lr = 300 w , r t = 60 k w , r rx = 30 k w . figure 3. longitudinal input impedance. v lot + v lor z lot = z lor = i lo longitudinal to metallic balance, b lme 4 0.2 khz < f < 3.4 khz, e lo b lme = 20 ? log v tr standard version normal polarity 50 70 db reversed polarity 50 65 db -/2 version normal polarity 60 70 db reversed polarity 55 65 db longitudinal to four wire balance,b lfe 4 0.2khz < f < 3.4khz e lo b lfe = 20 ? log v tx standard version normal polarity 50 70 db reversed polarity 50 65 db -/2 version normal polarity 60 70 db reversed polarity 55 65 db metallic to longitudinal balance, b mle 5 e tr b mle = 20 ? log , e rx = 0 v lo 0.2khz < f < 4.0khz 40 db f = 1.0 khz 53 db four wire to longitudinal balance,b fle 5e rx b fle = 20 ? log , e tr source removed v lo 0.2khz < f < 4.0khz 40 db f = 1.0 khz 53 db 2-wire return loss, r z l + z tr r = 20 ? log , note 5 z l - z tr 0.2khz f < 0.5khz 30 35 db 0.5khz f < 1.0khz 25 30 db 1.0khz f 3.4khz 15 21 db PBL3796, pbl 3796/2 tipx 27 ringx 28 v lot c i lo v lor 300 ohms 300 ohms e lo PBL3796, pbl 3796/2 tipx 27 ringx 28 rsn 19 vtx 21 r t r rx v tx r lt c r lr v tr e lo PBL3796, pbl 3796/2 tipx 27 ringx 28 rsn 19 vtx 21 r t r rx e rx r lt c e tr r lr v lo figure 2. overload level. 1/ w c << r l , pbl 3796 r l = 600 w , r t = 60 k w , r rx = 30 k w . PBL3796, pbl 3796/2 tipx 27 ringx 28 rsn 19 vtx 21 r t r rx e rx r l v tro i ldc c e l v txo (e l = 0) + + (e rx = 0) 4-109 pbl 3796 figure 6. frequency response, insertion loss, gain tracking, idle channel noise, thd, inter-modulation. 1/ w c << r l , r l = 600 w , r t = 60 k w , r rx = 30 k w . ref parameter fig conditions min typ max unit polarity reversal time, t pol normal to reversed polarity or 4 15 ms reversed to normal polarity tipx idle voltage, v ti normal polarity v bat = -48 v -5.0 -3.5 -2.0 v tipx to ringx idle voltage, vtro active and standby v bat =-48v r1=open loop standard version normal polarity 42 v reversed polarity -42 v -/2 version normal polarity 40 v reversed polarity -40 v 4-wire transmit port (vtx) overload level, v txo 2 load impedance > 20 k w , 3.1 3.5 v pk f = 1 khz, 1% thd, e rx = 0 9.0 10.1 dbu note 6 output offset voltage, d v tx -50 5 +50 mv output impedance, z tx 0.2khz f 3.4khz 6 20 w 4-wire receive port (rsn) rsn dc voltage, v rsn i rsn = 0 -10 0 +10 mv rsn impedance, z rsn 0.2khz f 3.4khz 3 20 w rsn current (i rsn ) to metallic 0.2khz f 3.4khz, 40 db loop current (i l ) gain, a rsn i l a rsn = i rsn frequency response two-wire to four-wire, g 2-4 6 0.3khz f 3.4khz -0.1 0.03 +0.1 db relative to 1.0 khz, 0 dbu e rx = 0 v, (note 7) four-wire to two-wire, g 4-2 6 0.3khz f 3.4khz -0.1 0.03 +0.1 db relative to 1.0 khz, 0 dbu e l = 0 v, (notes 8, 14) four-wire to four-wire, g 4-4 6 0.3khz f 3.4khz -0.1 0.06 +0.1 db relative to 1.0 khz, 0 dbu e l = 0 v, (notes 8, 14) insertion loss two-wire to four-wire, g 2-4 6 0 dbu, 1 khz, e rx = 0, (notes 7, 9) -0.15 0.1 +0.15 db four-wire to two-wire, g 4-2 6 0 dbu, 1 khz, e l = 0, (notes 8, 9) -0.15 0.1 +0.15 db four-wire to four-wire, g 4-4 6 0 dbu, 1 khz, e l = 0, (notes 8, 9) -0.15 0.1 +0.15 db gain tracking two-wire to four-wire (note 7) and 6 referenced to -10 dbu, 1 khz four-wire to two-wire (note 8) +3 dbu to -30 dbu -0.1 +0.1 db -30 dbu to -55 dbu 0.1 db PBL3796, pbl 3796/2 tipx 27 ringx 28 rsn 19 vtx 21 r t r rx e rx r l v tr i ldc c e l v tx + + rx tx 4-110 pbl 3796 figure 7. single-frequency out of band noise. resistance values in w , v lo = 1.6 ? v' lo 1/ w c << 100 w noise idle channel noise at two-wire 6 e rx = e l = 0, notes 2, 10, 14 (tipx-ringx) or four-wire (vtx) port c-msg weighting 10 14 dbrnc psophometrical weighting -80 -76 dbup single frequency out-of-band noise (note 11) metallic, v tr 7 12 khz f 1 mhz -58 -55 dbv longitudinal, v lo 7 12 khz f 90 khz -68 -63 dbv longitudinal, v lo 7 90 khz f 1 mhz -53 -50 dbv total harmonic distortion two-wire to four-wire, 6 0.3khz f 3.4khz -64 -50 db four-wire to two-wire 0 dbu, 1 khz test signal, note 2 intermodulation type 2f 1 - f 2 6 0.3 khz < f 1 , f 2 < 3.4 khz, level f 1 = level f 2 = -25 to 0 dbv f 1 1 nf 2 , f 2 1 nf 1 , note 2 two-wire to four-wire e rx = 0 -60 -50 db four-wire to two-wire e l = 0 -60 -50 db type f 1 50 hz 6 0.3khz < f 1 < 3.4khz level 50 hz = level f 1 - 14 db, level f 1 = -15 dbv to 0 dbv f 1 1 n ? 50 hz, note 2 two-wire to four-wire e rx = 0 -65 -50 db battery feed characteristics apparent battery voltage, e bap active state 47.5 50 52.5 v active, polarity reversal state -52.5 -50 -47.5 v feed resistance (r feed ) active and 4.75 5.00 5.25 ratio to programming resistance (r dc1 +r dc2 ) active, polarity reversal state conversion factor, k 1 r dc1 + r dc2 k 1 = r feed active state short circuit loop r dc1 +r dc2 = 2.5 k w 53 59 65 ma current, i lshact 145 i lshact = r dc1 + r dc2 active state loop current limiting r dc1 + r dc2 = 2.5 k w 46 ma threshold, i llimact 115 i llimact = , note 12 r dc1 + r dc2 active state line current v bat = -43.5v to -58.0v z l =2000 w 16 ma r dc1 +r dc2 =2.5k w stand-by state short circuit loop r dc1 +r dc2 = 2.5 k w 26 32 38 ma current, i lshsb 80 i lshsb = r dc1 + r dc2 stand-by state loop current limiting r dc1 + r dc2 = 2.5 k w 18 ma threshold, i llimsb 45 i llimsb = , note 12 r dc1 + r dc2 ref parameter fig conditions min typ max unit PBL3796, pbl 3796/2 tipx 27 ringx 28 67.5 c v' lo c v tr 67.5 56.25 20 20 i ldc + + 4-111 pbl 3796 figure 9. ring trip comparator. 2v < v < |v bat + 1|, i dt + i dr = i b , 2 v' dtr = d v dtr , v' dtr - v dtr d i b = r ref parameter fig conditions min typ max unit tip open circuit state tipx current, i ltlkto 8 tip open circuit state -100 5 100 m a v bat > v tto > 0 ringx current, i lrto 8 tip open circuit state r lrgnd = 0 w 23 35 50 ma r lrgnd = 2.5 k w v bat = -63 v 22 24 ma v bat = -48 v 16 18 ma ringx voltage, v rto 8i lrto < 20 ma v bat +1 v bat +4 v bat +6 v loop current detector loop current detector conversion factor i lthoff = k lthoff /r d on-hook to off-hook, k lthoff active, stand-by, polarity reversal state 395 465 535 v tip open circuit state. note 15 745 930 1115 v loop current detector conversion factor i lthon = k lthon /r d off-hook to on-hook, k lthon active, stand-by, polarity reversal state 348 410 472 v tip open circuit state. note 15. 655 820 985 loop current detector conversion factor active, stand-by and 20 55 90 v hysteresis, k lth polatiry reversal state. note 16. dial pulse distortion 10 pps, off-hook: 900 w 1 5 % on-hook: w ring trip comparator inputs (dt, dr) offset voltage, d v dtr 9v bat + 1 v < v dt , v dr < -2 v r = 0 k w -20 10 20 mv r = 200 k w -40 10 40 mv input offset current, d i b 9v bat + 1 v < v dt , v dr < -2 v 0.05 1 m a input bias current, i b 9v bat + 1 v < v dt , v dr < -2 v, 0.1 1 m a i b = (i dt + i dr )/2 input resistance v bat + 1 v < v dt , v dr < -2 v unbalanced, r dt , r dr 1m w balanced, r dtr 3 m w common mode range, v dt , v dr v bat +1 -2 v figure 8. tip open circuit state. PBL3796, pbl 3796/2 dt 25 dr 26 det 13 r gnd r v dtr i dt + dtr + v' i dr + v +i dr i dt PBL3796, pbl 3796/2 tipx 27 ringx 28 r lrgnd + v rto i lrto i ltlkto 4-112 pbl 3796 ref parameter fig conditions min typ max unit relay driver outputs (ringrly, testrly) on state voltage, v trly , v rrly i trly , i rrly = 25 ma 0 c < t amb < 25 c v cc - 2.0 v cc - 1.8 v 25 c < t amb < 70 cv cc - 1.8 v cc - 1.6 v cc - 1.0 v off state leakage current, i trly , i rrly v trly , v rrly = v bat 5 100 m a clamp voltage i trly , i rrly = 25 ma v bat - 3 v bat - 1 v digital inputs (c1-c4, e0, chclk) input low voltage, v il 0.8 v input high voltage, v ih 2.0 v input low current, i il v il = 0.4 v -0.4 ma input high current, i ih v ih = 2.4 v 40 m a digital output (det) output low voltage, v ol i ol = 1.0 ma 0.45 v output high voltage, v oh i oh = -0.1 ma 2.4 v resistive pull-up 12 15 18 k w switch mode regulator transistor output (l) switch transistor saturation voltage, v lsat i l = 100 ma, note 17 1.5 v leakage current, i llk v l = 0 v 200 m a switch mode regulator clock input (chclk) clock frequency, f chclk 253 256 259 khz rise and fall time 50 ns duty cycle ratio 46 54 % power supply rejection ratio (psrr) v cc to two-wire port and saturation guard off v cc to four-wire port 50 hz < f < 4 khz 35 db rejection ratio, psrr cc 4 khz < f < 50 khz 30 db saturation guard on 50 hz < f < 4 khz 20 db note 18 v ee to two-wire port and 50 hz < f < 4 khz 10 db v ee to four-wire port 4 khz < f < 50 khz 0 db rejection ratio, psrr ee note 18 v bat to two-wire port and 50 hz < f < 4 khz 25 db v bat to four-wire port 4 khz < f < 50 khz 20 db rejection ratio, psrr bat note 18 power supply currents (relay drivers off) v cc supply current, i cc on- or off-hook, active state 8 12 ma v ee supply current, |i ee | on- or off-hook, active state 6 9 ma v bat supply current, |i bat | on-hook, active state 3.5 6 ma power dissipation on-hook total dissipation, p onop v bat = -48 v, open circuit state 60 100 mw on-hook total dissipation, p onsb v bat = -48 v, stand-by state 190 250 mw on-hook total dissipation, p onact v bat = -48 v, active state 275 350 mw off-hook total dissipation, p off95 v bat = -48 v, active state 750 1000 mw r l = 600 w , r feed = 500 w note 19 temperature guard junction temperature at threshold, t jg 140 c temperature guard hysteresis, ? t jg 10 c 4-113 pbl 3796 notes 1. the overload level is specified at the two-wire port with the signal source at the four-wire receive port, i.e. e l = 0 in figure 2. 2. dbm is the ratio between power level p and a 1 mw reference power level, expressed in decibels, i.e. p dbm = 10 ? log 10 1 mw dbu is the ratio between voltage vrms and a 0.775 vrms reference, expressed in decibels, i.e. vrms dbu = 20 ? log 10 0.775 vrms dbu = dbm at impedance level 600 w dbv is the ratio between voltage v and a 1 v reference, expressed in decibels, i.e. v dbv = 20 ? log 10 1 v dbup is the ratio between voltage v p , measured via a psophometrical filter and a 0.775 vrms reference, expressed in decibels, i.e. v p dbup = 20 ? log 10 0.775 vrms dbrnc is the ratio between power level p c , measured via a c-message filter and a 1 pw reference power level, expressed in decibels, i.e. p c dbrnc = 10 ? log 10 1 pw 3. the two-wire impedance, z trx , is programmable by selection of external component values according to: z trx = z t / (g 2-4 ? a ) where: z trx = impedance between the tipx and ringx terminals z t = programming network between the vtx and rsn terminals g 2-4 = tipx-ringx to vtx gain, nom. = 1 (0 db 0.15 db) a = receive current gain, nominally = 100 (40 db 0.15 db) the fuse resistors r f add to the impedance presented by the slic at terminals tipx and ringx for a total two- wire impedance of z tr = z trx + 2r f . 4. normal polarity is defined as the tip lead being at a more positive potential than the ring lead. reversed polarity is defined as the ring lead being at a more positive potential than the tip lead. 5. higher return loss values can be achieved by adding a reactive component to r t , the two-wire terminating imped- ance programming resistor, e.g. by dividing r t into two equal halves and connecting a capacitor from the common point to ground. for r t = 60 k w the capacitance value is approximately 330 pf. 6. the overload level, v txo , is specified at the four-wire transmit port, vtx, with the signal source at the two-wire port. note that the gain from the two-wire port to the four- wire transmit port is g 2-4 = 1. 7. the level is specified at the two-wire port. 8. the level is specified at the four-wire receive port (rsn). 9. fuse resistors r f1 and r f2 impact the insertion loss as explained in the text, section transmission. the specified insertion loss is for r f1 = r f2 = 0 w . 10. the two-wire idle noise is specified with the port terminated in 600 w (r l ) and with the four-wire receive port grounded (e rx = 0, e l = 0; see figure 6). the four-wire idle noise at vtx is specified with the two- wire port terminated in 600 w (r l ). the four-wire receive port is grounded (e rx = 0, e l = 0; see figure 6). the idle channel noise degrades by approximately 5 db when the saturation guard is active. refer to section battery feed for a description of the saturation guard. 11. these specifications are valid for a longitudinal impedance of 90 w and a metallic impedance of 135 w . 12. when the loop current exceeds the limiting threshold the line feed changes from resistive feed (r feed = (r dc1 + r dc2 )/5) to nearly constant current feed. 14. this parameter degrades when the saturation guard is active. 15. refer to loop monitoring function, loop current detector - active state and loop current detector - tip open state. 16. the loop current detector threshold hysteresis is a function of the r d value. refer to note 15 above. 17. v lsat is the voltage across the saturated transistor, i.e. between terminals vbat and l. 18. power supply rejection ratio test signal is 100 mvrms (sinusoidal). 19. fuse resistor r f1 = r f2 = 0 w . pin description dip: 28-pin plastic dual in-line. plcc: 32-pin or 44-pin plastic leaded chip carrier. refer to figure 10. 44plcc 32plcc pdip symbol description 1 C C nc no internal connection. note 1. 2 1 1 gnd2 ground. no internal connection to gnd1. note 2. 3 2 2 vreg regulated negative voltage for power amplifiers. the switch-mode regulator inductor, filter capacitor and rc stabilization network connect to this pin. 4 3 3 vcc +5 v power supply. 4-114 pbl 3796 5 nc no internal connection. note 1. 5 tp tp is a thermal conduction pin tied to substrate (q bat ). note 3. 6 4 4 ringrly ring relay driver output. sources up to 80 ma from vcc. 7 6 5 testrly test relay driver output. sources up to 80 ma from vcc. 8 7 6 l switch-mode regulator drive transistor output. the 1 mh inductor and the catch diode connect to this pin. these components must be connected with shortest possible lead lengths. the catch diode, including connecting leads, must exhibit a low inductance to clamp effectively, when the regulator switch opens. 9 nc no internal connection. note 1. 10 8 7 vbat battery supply voltage. negative with respect to gnd2. 11 9 8 vqbat quiet battery. an external filter capacitor connects between this pin and gnd1 to provide filtered battery supply to signal processing circuits. 12 10 9 chs switch-mode regulator stabilization network input. from this pin a capacitor connects to gnd1 and a series rc network to vreg. 13 nc no internal connection. note 1. 14 11 10 chclk switch-mode regulator ttl compatible clock input. nominal frequency: 256 khz 15 nc no internal connection. note 1. 16 12 11 c4 c1, c2 , c3 and c4 are ttl compatible decoder inputs controlling the slic operating states. 17 13 nc no internal connection. note 1. 18 nc no internal connection. note 1. 19 14 12 e0 detector output enable. a logic high level enables the det output. a logic low level disables the det output. ttl compatible input. the dual-in-line package has the det output permanently enabled. 20 15 13 det detector output. inputs c1...c3 and e1 select the detector to be connected to this output. when det is enabled via e0 a logic low level indicates that the selected detector is tripped. the det output is open collector with internal pull-up resistor (15 kohms) to vcc. when disabled, det thus appears to be a resistor connected to v cc . 21 16 14 c2 refer to pin c4 description. 22 17 15 c3 refer to pin c4 description. 23 18 16 c1 refer to pin c4 description. 24 nc no internal connection. note 2. 25 rsg saturation guard programming input. a resistor, r sg , between pins rsg and vee adjusts the saturation guard for operation with v bat from -64 v to -46 v, see battery feed section. 26 19 17 rdc dc loop feed resistance is programmed by two resistors connected in series from this pin to the receive summing node, rsn. the resistor junction point is decoupled to gnd1 to filter noise and other disturbances before reaching the rsn input. v rdc polarity is negative for normal tip-ring polarity and positive for reversed tip-ring polarity. |v rdc | = |(|v tdc - v rdc |/20) - 2.5v|. 27 20&21 18 gnd1 ground. no internal connection to gnd2. note 2. 28 nc no internal connection. note 1. 29 22 19 rsn receive summing node. 100 times the current (dc and ac) flowing into this pin equals the metallic (transversal) current flowing between the tipx and ringx terminals. programming networks for feed resistance, 2-wire impedance, and receive gain connect to the receive summing node. 30 nc no internal connection. note 1. 31 23 20 vee -5 v power supply. 32 24 21 vtx transmit vf output. the ac voltage difference between tipx and ringx , the ac metallic voltage, is reproduced as an unbalanced gnd1 referenced signal at vtx with a gain of one. the two-wire impedance programming network connects between vtx and rsn. 33 nc no internal connection. note 1. 44plcc 32plcc pdip symbol description 4-115 pbl 3796 44plcc 32plcc pdip symbol description 34 25 22 hpt tip side (hpt) of ac/dc separation capacitor. 35 26 23 hpr ring side (hpr) of ac/dc separation capacitor. 36 nc no internal connection. note 1. 37 27 24 rd loop current detector programming resistor, r d , connects from rd to v ee . a filter capacitor c d may be connected from rd to gnd1. 38 28 25 dt inverting ring trip comparator input. 39 nc no internal connection. note 1. 29 tp tp is a thermal conduction pin tied to substrate (q bat ). note 3. 40 30 26 dr non-inverting ring trip comparator input. 41 tipx sense tipx sense is internally connected to tipx. tipx sense is used during manufacturing, but requires no connection in slic applications, i.e. leave open. 42 31 27 tipx the tipx pin connects to the tip lead of the 2-wire line interface via overvoltage protec- tion components, ring and test relays. 43 32 28 ringx the ringx pin connects to the ring lead of the 2-wire line interface via overvoltage protection components, ring and test relays. 44 ringx sense ringx sense is internally connected to ringx. ringx sense is used during manufacturing, but requires no connection in slic applications, i.e. leave open. notes 1. the gnd1 and gnd2 pins should be connected together via a direct printed circuit board trace. 2. pins marked nc are not internally connected. it is recommended to connect these pins to ground. 3. for 32 pin plcc, these pins (5 and 29) should be connected to v bat , heatsink. figure 10. pin configuration, top view. 32-pin or 44-pin j-leaded chip carrier (32 plcc, 44 plcc) and 28-pin dual-in-line. 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 testrly l nc chs nc chclk nc c4 nc nc dt rd nc hpr hpt nc vtx vee nc rsn 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 nc e0 det c2 c3 c1 nc rsg rdc gnd1 nc ringrly nc vcc vreg gnd2 nc ringx ringx tipx tipx dr vbat vqbat sense sense 44 plcc gnd2 ringrly testrly l chs chclk c4 ringx tipx dr dt rd hpr e0 det c2 vtx vee rsn gnd1 rdc c1 c3 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 12 13 14 21 20 19 18 17 16 15 22 hpt vreg vcc vbat vqbat 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 tp testrly l chs chclk c4 nc tp dt rd hpr hpt vtx vee rsn gnd1 14 15 16 17 18 19 20 4 3 2 1 32 31 30 det e0 c2 c3 c1 rdc gnd1 ringrly vcc vreg gnd2 ringx tipx dr vbat vqbat 32 plcc 4-116 pbl 3796 figure 11. pbl 3796 application example. + 38/25 40/26 42/27 34/22 35/23 43/28 6/4 7/5 10/7 2/1 3/2 8/6 11/8 12/9 dt dr tipx hpt hpr ringx ringrly testrly gnd2 l chs vbat vreg vqbat kr kt 25/- 37/24 31/20 4/3 32/31 29/19 26/17 16/11 22/15 21/14 23/16 20/13 19/- 17/12 14/10 27/18 rsg rd rsn rdc c4 c3 c2 c1 det e0 e1 chclk gnd1 vtx vcc vee -5v +5v 256 khz clock system control interface bat v ringing ring line test channel test tip (90 v rms + v bat ) bat v c ch2 c ch1 c q c flt l c bat c rc c hp c tc c rt c d c dc r dc2 r dc1 r t r b r fb r d r sg r 1 r 4 r 2 r 3 r f1 r rt r f2 r bat d 7 d 1 r ch d 5 k r k r k t k t k t k t low voltage high voltage u 1 u 2 combination codec/filter note 1 v t v rx r rx r tx c tisp bat v k1 k1 k2 k2 a g u 3 note 5 note 2 d 6 vee pbl 3796 nc v ee u1 pbl 3796 subcriber line interface circuit (slic) u2 combination codec/filter u3 secondary protection (e.g. texas instrument tisp pbl 1), note 7. r b resistor 27.4 k w 1% 1 /4 w r fb resistor dependent on application r rx resistor 42.2 k w 1% 1 /4 w r t resistor 82.5 k w 1% 1 /4 w r tx resistor 27.4 k w 1% 1 /4 w r ch resistor 909 w 2% 1 /4 w r 1 , r 3 resistor 200 k w 5% 1 /4 w r 2 resistor 909 k w 5% 1 /4 w r 4 resistor 1.21 m w 5% 1 /4 w r d resistor 51.1 k w 5% 1 /4 w r dc1 , r dc2 resistor 1.24 k w 5% 1 /4 w r sg resistor note 3 5% 1 /4 w r rt resistor 150 w 5% 2 w r bat resistor note 4 r f1 , r f2 resistor 40 w 1% r f1 /r f2 ratio match (e.g. ericsson components pbr 51- series) c bat capacitor0.47 m f 20% 100v c tisp capacitor 220 nf 20% 100v c ch1 capacitor 47 nf 10% 100v c ch2 capacitor1500 pf 10% 100v c d capacitor6200 pf 20% 10v c dc capacitor 1.2 m f 10% 10v c flt capacitor0.47 m f 10% 100v c hp capacitor0.22 m f 10% 100v c q capacitor 0.33 m f 20% 100v c rt capacitor 0.39 m f 20% 100v c tc , c rc capacitor 2200 pf10% 100v d 1 diode 100 v100 ma 10 ns (e.g. 1n4448) d 6 diode note 6 d 7 diode 100 v500 ma l inductor 1 mh 10%r 3 15 w (e.g. siemens b78108-s1105-j, j. w. miller 9220-28, nytronics rfc-s, or ericsson reg 522 7103) k t relay, test 4c contacts k r relay, ring 2c contacts notes 1 the ringtrip network may alternatively be located on the ring lead side. the ringtrip network may also be configured for balanced ringing as shown in figure 20. 2 it is recommended to connect pins marked "nc" (44- pin package pins # 1, 5, 9, 13, 15, 18, 24, 28, 30, 33, 36 & 39) to ground. 3. rsg is open circuit for v bat = -48 v and shorted to v ee for v bat = -63 v. for intermediate battery voltages, calculate as described in the section, battery feed, case 2". 4. r bat for one line is recommended to be 5,6 w 5% 1/ 4w. however the resistor can be shared between several lines, for instance 1 w 5% 1w for eight lines. 5. the ground terminals of the secondary protection should be connected to the common ground on the printed board assembly with a track as short and wide as possible, preferrable a ground plane. 6. for diode type, refer to section "power-up sequence". 7. texas instrument tisp pbl2 should be used when pbl 3796 is programmed for a maximum line current exceeding 60 ma. 4-117 pbl 3796 1 z t = 100 ? (900 + - 2 ? 40) j w ? 2.16 ? 10 -6 1 = 82 ? 10 3 + j w ? 21.6 ? 10 -9 i.e. z t = 82 k w in series with 21.6 nf. it is always necessary to have a high ohmic resistor in parallel with the capacitor. this gives a dc-feedback loop for low frequency which ensure stability and reduces noise. two-wire to four-wire gain the two-wire to four-wire gain, g 2-4 , can be obtained from (1) and (2) with v rx = 0: v tx z t /100 g 2-4 == v tr z t /100+2r f four-wire to two-wire gain the four-wire to two-wire gain, g 4-2 , is derived from (1), (2) and (3) with e l = 0: v tr z t z l g 4-2 == -? v rx z rx z t /100 + 2r f + z l functional description and applications information transmission overview a simplified ac model of the transmission circuits is shown in figure 12. neglecting the impact of the filters in figure 12 for frequencies from 300 hz to 3.4 khz (i.e. filter gain = 1), circuit analysis yields: v tr = v tx + i l ? 2r f (1) v tx v rx i l + = (2) z t z rx 100 v tr = e l - i l ? z l (3) where: v tx is the ground referenced, unity gain version of the ac metallic (transver- sal) voltage between the tipx and ringx terminals, i.e. v tx = 1 ? v trx . v tr is the ac metallic voltage between tip and ring. e l is the line open circuit ac metallic voltage. i l is the ac metallic current. r f is the overvoltage protection current limiting resistor. z l is the line impedance. z t is the programming network for the tipx to ringx impedance. z rx controls the four-wire to two-wire gain. v rx is the analog ground referenced receive signal. from equations (1), (2) and (3) expressions for two-wire impedance, two- wire to four-wire gain, four-wire to two- wire gain and four-wire to four wire gain may be derived. two-wire impedance to calculate z tr , the impedance presen- ted to the 2-wire line by the slic, including the resistors r f , let v rx = 0. from (1) and (2): z t z tr =+ 2r f 100 since z tr and r f are known z t may be calculated from z t = 100 ? (z tr - 2r f ) example: calculate z t to make the terminating impedance z tr = 900 w in series with 2.16 m f. r f = 40 w . using the expression above four-wire to four-wire gain the four-wire to four-wire gain, g 4-4 , is derived from (1), (2) and (3) with e l = 0: v tx z t z l + 2r f g 4-4 == -? v rx z rx z t /100 + 2r f + z l hybrid function the pbl 3796 slic forms a particularly flexible and compact line interface when used together with a siemens codec filter circuit (sicofi) or other similar programmable codec/filter. the sicofi allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. the sicofi also permits the system controller to adjust transmit and receive gains as well as terminating impedance. refer to sicofi or similar programmable codec/filter data sheets for design information. the hybrid function in an implementa- tion utilizing the uncommitted amplifier in figure 13. hybrid function. figure 12. simplified ac transmission circuit. a: lowpass filter, -3db @ ? 34 khz b: highpass filter, -3db @ ? 1.8 hz c: lowpass filter, -3db @ ? 1.8 hz * ac-dc separation filter frequency is set by c hp 27 28 tipx ringx ring tip 1 -1/20 1 -1/5 17 19 21 rdc rsn vtx r dc2 r dc1 z t z rx v tx v rx c dc r f r f -i l /500 -i l /500 -i l -i l v trx v tr z tr z l e l + + a b* c a pbl 3796, pbl 3796/2 + i l /100 + + x 500 x 500 combination codec/filter -+ pbl 3796, pbl 3796/2 z t z rx z b r tx r fb 19 21 rsn vtx v t v rx 4-118 pbl 3796 example: z tr = z l = 600 w (r l ) in series with 2.16 m f (c l ) r f = 40 w , r tx = 27.4 k w , g 4-2 = -1. calculate z b . using the z b formula above: z rx 2z l z b = {z l = z tr } = r tx ?? = z t z l + 2r f z l = {g 4-2 = -1} = r tx ?= z l + 2r f 1 + j w ? r l ? c l = r tx ? 1 + j w ? (r l + 2r f ) ? c l a network consisting of r b1 in series with the parallel combination of r b and c b has the same form as the required balance network, z b . basic algebra yields: r l r b1 = r tx ? = 25.2 k w r l + 2r f a conventional codec/filter combination is shown in figure 13. via impedance z b a current proportional to v rx is injected into the summing node of the combination codec/filter amplifier. as can be seen from the expression for the four-wire to four-wire gain a voltage proportional to v rx is returned at vtx. this voltage is converted by r tx to a current flowing into the same summing node. these currents can be made to cancel each other by letting: v tx v rx += 0 (e l = 0) r tx z b substituting the four-wire to four-wire gain expression, g 4-4 , for v rx /v tx yields the formula for the balance network: v rx z b = - r tx ?= v tx z rx z t /100 + 2r f + z l = r tx ?? z t z l + 2r f 2r f r b = r tx ? = 2237 w r l + 2r f (r l + 2r f ) 2 ? c l c b = = 0.95 m f r tx ? 2r f longitudinal impedance a feedback loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. therefore longitudinal disturbances will appear as longitudinal currents and the tipx and ringx terminals will experien- ce very small longitudinal voltage excursions well within the slic common mode range. this is accomplished by comparing the instantaneous two-wire longitudinal voltage to an internal reference voltage, v loref . as shown below, the slic appears as 20 w to ground per wire to longitudinal disturbances. it should be noted, that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. from figure 14 the longitu- dinal impedance can be calculated: v lo r lo = = 20 w i lo 100 where: v lo is the longitudinal voltage i lo is the longitudinal current r lo = 2 k w sets the longitudinal impedance ac - dc separation capacitor the high pass filter capacitor connected between terminals hpt and hpr provides separation between circuits sensing tipx-ringx dc conditions and circuits processing vf signals. the recommended c hp capacitance value of 220 nf will position the 3 db break point at 1.8 hz. capacitor c tc and c rc the capacitors designated c tc and c rc in figure 11, connected between tipx and ground as well as between ringx and ground, are recommended as an addition to the overvoltage protection network. very fast transients, appearing on tip and ring, may pass by the diode and scr clamps in the overvoltage protection and could damage the slic. c tc and c rc short such very fast transients to ground. the recommended value for c tc and c rc figure 14. longitudinal feedback loop. v loref = (v tip + v ring )/2 (without any longitudinal voltage component). figure 15. battery feed. + - pbl 3796, pbl 3796/2 1 1 r r r hp /2 r hp /2 r lo = 2 kohms v lo v loref v lo + v loref i lo /100 i lo c hp 27 22 23 28 ringx hpr hpt tipx i lo i lo v lo v lo i lo 1 absolute value + - 1/20 +1 normal -1 reversed p -2.5 v i ldc /100 rsn 19 rdc 17 v reg (normal) gnd2 (reversed polarity) v reg (reversed polarity) gnd2 (normal) v trdc v trxdc + + tip ring r f r f 28 27 ringx tipx pbl 3796, pbl 3796/2 r dc2 r dc1 c dc i ldc i ldc 4-119 pbl 3796 is 2200 pf. higher capacitance values may be used, but care must be taken to prevent degradation of either longitudi- nal balance or return loss. c tc and c rc contribute a metallic impedance of 1/( p f c tc ) ? 1/( p f c rc ), a tipx to ground impedance of 1/(2 p f c tc ) and a ringx to ground impedance of 1/(2 p f c rc ). battery feed overview the pbl 3796 slic synthesizes a resistive battery feed system with loop current limiting on short loops. a switch- mode regulator efficiently down-converts the battery supply voltage to reduce power dissipation. the down-converted voltage is applied to the line drive amplifiers and is automatically adjusted to be precisely enough to feed the loop current as well as to allow distortion free vf signal transmission. the synthesized battery feed is a 50 v source in series with a programmable feed resistance. the apparent 50 v battery is independent of actual supply voltage connected to the slic. the slic feed resistance is set via scaled, external resistors. for short loops the battery feed is quasi-constant current. the battery feed polarity can be set to either normal or reversed polarity via the slic digital control inputs. to permit the line drive amplifiers to operate without signal distortion even on high resistance or open circuit loops, a saturation guard circuit limits the loop voltage, when the tip to ring dc voltage approaches the available battery supply voltage. with the slic set to the stand-by state, power is further conserved by limiting the short circuit loop current to approximately 55% of the active state short circuit current. the following paragraphs describe the battery feed circuit in detail. at the end of this section a paragraph, battery feed circuit programming procedure, summa- rizes the few simple calculations neces- sary to program the battery feed. case 1: slic in the active or active polarity reversal state; |v trdc | < v sgref , |v bat | > v sgref + 12 v in the active state c3, c2, c1 = 0, 1, 0 and in the active polarity reversal state c3, c2, c1 = 1, 1, 0. the battery feed control loop is shown in block diagram form in figure 15. for tip to ring dc voltages less than the satura- tion guard reference voltage, v sgref (refer to case 2) and for loop currents less than the loop current limiting threshold, i llimact , the following expression, obtained from the block diagram for r f = 0, describes the loop feed: ( v trdc 1 -2.5 ) p 1 100 = -i ldc 20 r dc1 + r dc2 where v trdc is the tip to ring dc voltage i ldc is the dc loop current r dc1 , r dc2 are the external feed resis- tance programming resistors p = 1 for normal polarity and p = -1 for reversed polarity by defining the feed resistance r feed as r dc1 + r dc2 r feed = 5 and substituting into the above expression the familiar resistive battery feed formula is obtained: 50 - |v trdc | i ldc = p ? r feed where 50 v is the apparent battery voltage, e bap . the loop current may also be described as a function of loop resistance r l since v trdc = i ldc ? r l : 50 i ldc = p ? r l + r feed the loop current is limited when exceeding i llimact , the loop current limiting threshold. 115 i llimact = r dc1 + r dc2 at i llimact the loop current is 0.5 ma less than predicted by the resistive battery feed formula described earlier in this section. at the loop current limiting threshold, the loop resistance is 27 - (r dc1 + r dc2 ) ? 10 -4 r llimact = 5 ? 10 -4 + 115/(r dc1 + r dc2 ) at short circuit, i.e. r l = 0 ohm, the figure 16. battery feed example. r dc1 = r dc2 = 1.25 k w , i.e. r feed = 2 ? 250 w v bat = -48 v curve abcd: active state curve aef: stand-by state 0 10 20 30 40 50 60 0 10203040 v trdc i l [ma] a b f c d e 4-120 pbl 3796 switch control 12 6 gnd2 v reg l vqbat 9 vbat chs chclk (256 khz) 10 v ref v reg gnd2 d 1 l c bat c flt c ch1 c q c ch2 r ch pbl 3796, 78 v bat pbl 3796/2 v qbat case 3: slic in the stand-by or stand- by polarity reversal state; |v trdc | < v sgref , |v bat | > v sgref + 12 v the stand-by operating states reduce power dissipation while the line is idle. the loop feed in the stand-by state (c3, c2, c1 = 0, 1, 1) and in the stand-by polarity reversal state (c3, c2, c1 = 1, 1, 1) is similar to the active state loop feed, but with lower loop current limits. the stand-by state loop current limiting threshold is 45 i llimsb = r dc1 + r dc2 the short circuit stand-by state loop current is 80 i lshsb = r dc1 + r dc2 stand-by state loop resistance at the limit threshold, i llimsb , is 41 - (r dc1 + r dc2 ) ? 10 -4 r llimsb = 5 ? 10 -4 + 45/(r dc1 + r dc2 ) stand-by state loop currents between i llimsb and i lshsb may be calculated from 1 r l i ldc ? 80 - 35 ? r dc1 + r dc2 ? r llim ? in figure 16, pbl 3796 battery feed examples, this corresponds to curve segment ef. case 4: slic in the tipx open circuit state. in the tipx open circuit state c3, c2, c1 = 1, 0, 0. refere to figure 8. in this state the tipx terminal is set to high impedan- ce, >150 k w . the ringx terminal sinks a current |i lrto | > 20 ma until the v bat voltage is approached, whereafter the ringx terminal changes to become a constant voltage source. the constant voltage mode ringx current can be calculated from |v bat + 4| |i lrto | = r lrgnd where: r lrgnd is the resistance between ground and ring lead. c dc capacitor refer to the battery feed block diagram, figure 15. the battery feed programming resistors r dc1 and r dc2 together with capacitor c dc form a low pass filter, which removes noise and vf signals from the battery feed control loop. the recommen- ded 3 db break point frequency is 160 hz < f 3db < 240 hz. the c dc capacitance figure 17. switch mode regulator. case 2: slic in the active or active polarity reversal state; |v trdc | > v sgref , |v bat | > v trdc +12v in the active state c3, c2, c1 = 0, 1, 0 and in the active polarity reversal state c3, c2, c1 = 1, 1, 0. when the tip to ring dc voltage approaches the v bat supply voltage, a circuit named saturation guard limits the two wire voltage to a small additional increase beyond the saturation guard threshold, v sgref . this is to maintain distortion free vf transmission through the line drive amplifiers. the saturation guard feature makes on-hook transmission possible. the tip to ring voltage at which the saturation guard becomes active, v sgref , can be calculated from v r sg f sg re , , , = - + 32 0 1 0 921 273 where v sgref is in volts for r sg in kohms r sg is a resistor connected between terminal rsg and -5v. note that the rsg terminal is available only on the 44-pin surface mount package. the 28-pin dual-in-line and 32-pin surface mount package have the saturation guard internally set to v sgref = 32,0v r sg = open circuit yields v sgref = 32,0v r sg = 0 ohm yields v sgref = 48,3v the loop current, i ldc , as a function of the loop voltage, v trdc , for v trdc > v sgref is described by i vv v rr ldc sg f trdc sg f dc dc = - + - + re re ()/ 120 50 5 12 from which the open loop voltage (i l = 0) is calculated to vi v v rr trdc ldc sg f sg f dc dc (@ ) () ()/ re re == + - + 0 120 50 5 12 the open circuit voltage is then, for a programmed feed resistance of 2?250 w , 36,3v for r sg = open circuit and 48,7v for r sg = 0 w . in figure 16, PBL3796 battery feed examples, curve segment ab is described by case 2. loop current is limited to 145 i lshact = r dc1 + r dc2 loop currents between i llimact and i lshact may be calculated from 1 r l i ldc ? 145 - 30 ? r dc1 + r dc2 ? r llimact ? in figure 16, pbl 3796 battery feed examples, curve segments bc and cd are described by case 1. 4-121 pbl 3796 when the loop voltage exceeds v sgref , the loop feed converts to nearly constant voltage feed with a resistive feed characteristics of approximately 120 w . after calculating r dc1 ,and r dc2 , verify the resulting short circuit loop current i rr lshact dc dc = + 145 12 3. calculate c dc from 1 11 c dc =?+ 2 p ? f 3db ? r dc1 r dc2 ? where f 3db = 200 hz 4. recommended switch mode regulator component values: l = 1 mh 10 %; c flt = 0.47 m f 10%, 100 v; d 1 = 1n4448 (or equivalent), r ch = 909 w 2%, 0.25 w; c ch1 = 0.047 m f 10%, 100 v; c ch2 = 1500 pf 10%, 100 v. loop monitoring functions overview the pbl 3796 slic contains two detectors: the loop current and the ring trip detector. these two detectors report their status via the shared det output. the detector to be connected to the det output is selected according to the logic states at the control inputs c1, c2, c3. enable input e0 sets the det output to either active or high impedance state. loop current detector - active state and stand-by state active state (c3, c2, c1 = 0, 1, 0), active polarity reversal state (c3, c2, c1 = 1, 1, 0), stand-by state (c3, c2, c1 = 0, 1, 1), and stand-by polarity reversal state (c3, c2, c1 = 1, 1, 1). the loop current value at which the loop current detector changes state is programmable by calculating a value for resistor r d . r d connects between terminals rd and vee. figure 18 shows a block diagram for the loop current detector. the two-wire interface produces a current, i rd , flowing out of pin rd: |i lt - i lr ||i l | i rd = 0.5 ? = 300 300 where i lt and i lr are currents flowing into value is then calculated from: 1 11 c dc =?+ 2 p ? f 3db ? r dc1 r dc2 ? note that r dc1 = r dc2 yields minimum c dc capacitance value. switch mode regulator the switch mode regulator down- converts the v bat supply voltage to a value, which is just enough for the line drive amplifiers to feed the required loop current and maintain transmission quality. since the voltage conversion efficiency is high and the minimum required voltage drop across the line drive amplifiers is low, a significant power dissipation reduction is realized. a 2 x 400 w resistive battery feed with 200 w line resistance and -48 v battery will have 1.84 w dissipated in the line feed resistors. the pbl 3796 set up for the same 2 x 400 w feed and with the same 200 w line resistance and -48 v, v bat would generate only 0.46 w in the line feed circuits (90% power conversion efficiency), i.e. a 1.38 w or 75% reduc- tion in line card power dissipation. refer to figure 17 for a block diagram of the switch mode regulator. vbat is the input voltage, which the regulator converts to vreg with high efficiency. v reg powers the line drive amplifiers. the switch mode regulator adjusts its v reg output to be equal to the reference voltage, v ref . the reference voltage is derived from the tipx to ringx dc metallic voltage according to v ref = -(|v trdc | + v bias ) where v bias is approximately 12 v. since v bias is the voltage drop across the line drive amplifiers, the slic power loss is greatly reduced compared to supplying the amplifiers directly from the v bat supply. the battery supply voltage, |v bat |, must be larger than |v reg |, i.e. |v bat | 3 |v trdc | + v bias . if this condition is not met, the tip to ring voltage will be limited by the slic according to |v trdc | = |v bat | - v bias . although the slic continues to function, this mode of operation should be avoided due to increased noise and a much reduced v bat to transmission ports rejection ratio. to minimize noise as well as battery feed circuit power dissipation on long loops the switch mode regulator is automatically turned off for tip to ring dc voltages exceeding a threshold value of approximately v sgref - 1v. with the regulator disabled, the v bat supply voltage is passed on to the vreg input without being down-converted. the inductor, l, should be 1 mh with a series resistance larger than 15 w . a saturated inductor with less than 15 w of series resistance may damage the slic due to excessive regulator switch current. c flt , 0.47 m f, is the regulator output filter capacitor. the catch diode, d 1 , (e.g.1n4448) must withstand 70 v reverse voltage, conduct an average of 50 ma (150 ma peak) and turn off in less than 10 nsec. c ch1 , c ch2 and r ch make up a compen- sation network for an internal voltage comparator. values are given in the applications example, figure 11. the components associated with the switching regulator must be connected via the shortest possible pcb trace lengths. other circuits should be kept isolated from this area. the l terminal voltage variations are large and very fast. to avoid interference the inductor and the catch diode should be located directly at this terminal. inductors with closed magnetic path core (e.g. toroid, pot core) will reduce interference originating from the inductor. battery feed circuit programming procedure extracting the key elements from the preceeding description results in the following step-by-step procedure. 1. establish the battery feed require- ments. maximum loop resistance, including fuse resistors r f1 and r f2 , r lmax = ? loop current at the maximum loop resistance, i lmin = ? slic supply voltage, vbat = ? 2. calculate the feed resistance programming components r dc1 and r dc2 from rr i r dc dc lmin lmax 12 50 25 ==- [], note that the above calculation for r dc1 , r dc2 is valid only for i lmin ?r lmax 4-123 pbl 3796 therefore, by sampling the det output, a software routine can discriminate between on-hook and off-hook through examination of the duty cycle. full removal of the ringing frequency from the dt input while maintaining ringtrip within required time limits (approximately < 100 ms) usually mandates a second order filter rather than the first order shown in figure 20. the software approach minimizes the number of line card components. in the balanced ringing system shown in figure 19, r 1 and r 2 are the loop current sensing resistors. with the telephone on-hook, no dc loop current flows to cause a dc voltage drop across resistors r 1 and r 2 . voltage dividers r b2 , r 4 and r b1 , r 3 bias the ringtrip compara- tor input dt to be more positive than dr. with the telephone off-hook during ringing dc loop current will flow, causing a voltage drop across resistors r 1 and r 2 , which in turn will make comparator input dt more negative than dr, setting the det output to logic low level, indicating ringtrip condition. capacitors c rt1 and c rt2 filter the ring voltage at the comparator inputs. for 20 hz ringing it is suitable to calculate these capacitors for a time constant of t = 50 ms, i. e. 11 c rt1 = t ? + ? r b2 r 4 ? detector output, det the loop current detector and ringtrip comparator share a common output, det. the det output is open collector with internal pull-up resistor to v cc . via on the other wire. a ring relay, energized by the slic ring relay driver, connects the ringing source to tip and ring. for unbalanced ringing systems the loop current sensing resistor may be placed either in series with the ringing generator or in series with the return lead to ground. figures 19 and 20 show examples of balanced and unbalanced ringing systems. for either ringing system the ringtrip detection function is based on a polarity change at the inputs dt and dr of the ringtrip comparator. in the unbalanced case the dc voltage drop across resistor r rt is zero as long as the telephone remains on-hook. with the telephone off-hook during ringing, dc loop current will flow, causing a voltage drop across r rt . the r rt voltage is applied to the comparator input dt via resistor r 3 . r 4 shifts the voltage level to be within the comparator common mode range. c rt removes the ac component of the ringing signal. r 1 and r 2 establish a bias voltage at comparator input dr, which is more negative than dt when the telephone is on-hook and is more positive than dt when the telephone goes off-hook during ringing. complete removal of the ringing signal ac component at the dt input may not be necessary. some residual ac component at the dt input may under certain operating conditions cause the det output to toggle between the on-hook and off-hook states at the ringing frequency. however, with the telephone off-hook the det output will be at logic low level for more than half the time. control inputs c1 through c3 one of the two detectors is selected to be connected to the det output. with enable input e0 set to logic high level, the det output is activated. in the det active state a logic low level indicates a triggered detector condition and a logic high level reports a non-triggered detector. with e0 set to logic low level, the det output is set to its high impedance state, i.e. connected to v cc via the internal pull-up resistor. relay drivers the pbl 3796 slic contains two identical drivers for test and ring relays. the drivers are pnp transistors in open collector configuration, designed to drive 80 ma from the v cc supply. each driver has an internal inductive kick-back clamp diode. the relay coil may be connected to negative supply voltages ranging from ground to v bat . control input c4 activates the test relay driver. control inputs c1, c2 and c3 are used to operate the ring relay. control inputs overview the pbl 3796 slic has four ttl compatible control inputs, c1 through c4. a decoder in the slic interprets the control input logic conditions and sets up the commanded operating state. c1 through c3 allow for eight operating states. the c4 control input acts directly on the test relay driver. the control inputs interface with programmable codec/filters, e.g. slac, sicofi, combo ii without any figure 20. ring trip network, unbalanced ringing. pbl 3796, pbl 3796/2 26 dr 25 dt r 1 r 2 r 4 r 3 r rt c rt e rg v bat ring tip k r + - subscriber line ring trip comparator 4-124 pbl 3796 than the threshold value i llimsb = 45 / (r dc1 + r dc2 ). for loop currents less than i llimsb , battery feed is identical to the active state loop feed. the loop current detector is connected to the det output. tipx open circuit state (c3, c2, c1 = 1, 0, 0) the tipx power amplifier presents a high impedance to the line. the ringx terminal is active and sinks current. the loop current detector is connected to the det output. the detection threshold for the on-hook to off-hook transition is i lrthoffto = (1.55 ? 600) / r d . the ringx terminal is able to sink up to 35 ma from ground. reserved state (c3, c2, c1 = 1, 0, 1) this state has no assigned function. active polarity reversal state (c3, c2, c1 = 1, 1, 0) tipx and ringx polarity is reversed from the active state: ringx is the terminal closest to ground and sources loop current while tipx is the more negative terminal and sinks current. polarity reversal transition time is approximately 4 msec.. the loop current detector is connected to the det output. signal transmission is normal. the loop current is limited to 145 / (r dc1 + r dc2 ). stand-by polarity reversal state (c3, c2, c1 = 1, 1, 1) polarity reversal as described under state c3, c2, c1 = 1, 1, 0 and stand-by as described under state c3, c2, c1 = 0, 1, 1. enable input e0 sets the det output to active state, when at logic high level and to high impedance state when at logic low level. table 2 summarizes the above description of the enable input. overvoltage protection the pbl 3796 slic must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. refer to maximum ratings, tipx and ringx terminals, for maximum allowable continuous and transient voltages that may be applied to the slic. the circuit shown in figure 12 utilizes series resistors together with a interface components. via serial i/o ports on the programmable codec/filter devices a micro processor can communicate with the slic. in designs utilizing conventional codec/filters without control latches, the line card logic must contain the neccessary latches for inputs c1 through c4. table 1 contains a summary descrip- tion of the control inputs. test relay control (c4) with c4 set to logic low level the test relay driver (testrly) is activated. c4 set to logic high level causes the relay driver to be de-energized. the test relay driver is controlled exclusively by c4 and is independent of the c1, c2 and c3 logic levels. open circuit state (c3, c2, c1 = 0, 0, 0) in the open circuit state both the tipx and ringx power amplifiers present a high impedance to the line. the loop current detector is not active in this state. ringing state (c3, c2, c1 = 0, 0, 1) the ring relay driver (ringrly) is activated and the ring trip comparator is connected to the detector output (det) . the tipx and ringx terminals are in the high impedance state and signal trans- mission is inhibited. active state (c3, c2, c1 = 0, 1, 0) tipx is the terminal closest to ground potential and sources loop current, while ringx is the more negative terminal and sinks loop current. signal transmission is normal and the loop current detector is gated to the det output. stand-by state (c3, c2, c1 = 0, 1, 1) in the stand-by state the short circuit loop current is limited to a maximum of i lshsb = 80 / (r dc1 + r dc2 ). loop current limiting starts to take effect for currents larger enable e0 det output state active detector state # 1 0 high impedance none 2 1 active loop current or ringtrip. note 1 notes 1. the loop current detector or the ring trip comparator is selected via c3, c2, c1 (state # 2 selects the ringtrip comparator) table 2. enable input. table 1. pbl 3796 operating states. c4 c3 c2 c1 operating state active detector state # note 1 1 x 0 0 0 open circuit ring trip comparator 2 x 0 0 1 ringing ring trip comparator 3 x 0 1 0 active loop current 4 x 0 1 1 stand-by loop current 5 x 1 0 0 tip open loop current 6 x 1 0 1 reserved none 7 x 1 1 0 active polarity reversal loop current 8 x 1 1 1 stand-by polarity reversal loop current notes 1. control input c4 logic state (x) affects only the test relay driver and does not change the slic operating state. c4 at logic low level activates the test relay driver. c4 at logic high level turns the test relay driver off. 4-125 pbl 3796 programmable overvoltage protector (e g texas instrument tisp pbl1), serving as a secondary protection. the protection network in figure 9 is designed to meet requirements in itu-t k20, table 1. the tisp pbl1 is a dual forward- conducting buffered p-gate overvoltage protector. the protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage,v bat ). as the protection voltage will track the negative supply voltage the overvoltage stress on the slic is minimized. positive overvoltages are clamped to ground by an internal diode. negative overvoltages are initially clamped close to the slic negative supply rail voltage. if sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition, clamping the overvoltage close to ground. a gate decoupling capacitor, c tisp is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. without the capacitor even the low inductance in the track to the v bat supply will limit the current and delay the activation of the thyristor clamp. the fuse resistors r f serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. ericsson components ab offers a series of thick film resistors networks (e g pbr 51- series and pbr 53-series) designed for this application. also devices with a built in resetable fuse function is offered (e g pbr 52-series) including positive temperature coefficient (ptc) resistors, working as resetable fuses, in series with thick film resistors. note that it is important to always use ptcs in series with resistors not sensitive to temperature, as the ptc will act as a capacitance for fast transients and therefore the ability to protect the slic will be reduced. if there is a risk overvoltages on the v bat terminal on the slic, then this terminal should also be protected. over-temperature protection a ring lead to ground short circuit fault condition, as well as other improper operating modes, may cause excessive slic power dissipation. if junction temperature increases beyond 140 c, the temperature guard will trigger, causing the slic to be set to a high impedance state. in this high impedance state power dissipation is reduced and the junction temperature will return to a safe value. once below 130 c junction temperature the slic is returned back to its normal operating mode and will remain in that state assuming the fault condition has been removed. power-up sequence the voltage at pin vbat sets the substrate voltage vqbat (supplied internally from vbat through a resistor), which must at all times be kept more negative than the voltage at any other terminal. this is to maintain correct junction isolation between devices on the chip. to prevent possible latch-up, the correct power-up sequence is to connect ground and v bat , then other supply voltages and signal leads. should the v bat supply voltage be absent, a diode with a 2 a current rating, connected with its cathode to vee and anode to vqbat, ensures the presence of the most negative supply voltage at the vqbat pin. the v bat voltage should not be applied at a faster rate than dv bat /dt = 4 v/ m sec, e.g. a time constant formed by a 5.1 ohm resistor in series with the vbat pin and a 0.47 microfarad capacitor from the vbat pin to ground. one resistor may be shared by several slics. printed circuit board layout care in pcb layout is essential for proper function. the components connecting to the rsn input should be placed in close proximity to that pin, such that no interference is injected into the rsn terminal. a ground plane surrounding the rsn pin is advisable. the c hp capacitor should be placed close to terminals hpt and hpr to avoid unwanted disturbances. the switch mode regulator compo- nents must be located near the pins to which they connect. it is particularly important that the catch diode and the inductor are connected via shortest possible trace lengths. ground terminals gnd1 and gnd2 should be connected via a direct pcb trace at the device location. ordering information package temp range part no. plastic dip 28-p 0 to 70 c pbl 3796n plcc 44-pin 0 to 70 c pbl 3796qn plcc 44-pin 0 to 70 c pbl 3796/2qn plcc 32-pin 0 to 70 c pbl 3796rn plcc 32-pin 0 to 70 c pbl 3796/2rn 4-126 pbl 3796 specifications subject to change without notice. 1522 pbl 3796 uen rev. a ? ericsson components ab april 1997 this product is an original ericsson product protected by us, european and other patents. ericsson components ab s-164 81 kista-stockholm, sweden telephone: (08) 757 50 00 information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson components ab. these products are sold only according to ericsson components ab' general conditions of sale, unless otherwise confirmed in writing. |
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